From a82e98d473fd212316ea5aa078a7588324b020e5 Mon Sep 17 00:00:00 2001 From: Paul Durrant Date: Fri, 15 Nov 2013 11:02:17 +0100 Subject: [PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE Intercepting this MSR is pointless - The swapgs instruction does not cause a vmexit, so the cached result of this is potentially stale after the next guest instruction. It is correctly saved and restored on vcpu context switch. Furthermore, 64bit Windows writes to this MSR on every thread context switch, so interception causes a substantial performance hit. Signed-off-by: Paul Durrant Signed-off-by: Andrew Cooper Reviewed-by: Tim Deegan Acked-by: Jun Nakajima --- xen/arch/x86/hvm/vmx/vmcs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 290b42f7a9..4aab971992 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -950,6 +950,7 @@ static int construct_vmcs(struct vcpu *v) vmx_disable_intercept_for_msr(v, MSR_FS_BASE, MSR_TYPE_R | MSR_TYPE_W); vmx_disable_intercept_for_msr(v, MSR_GS_BASE, MSR_TYPE_R | MSR_TYPE_W); + vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE, MSR_TYPE_R | MSR_TYPE_W); vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_CS, MSR_TYPE_R | MSR_TYPE_W); vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_ESP, MSR_TYPE_R | MSR_TYPE_W); vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_EIP, MSR_TYPE_R | MSR_TYPE_W); -- 2.30.2